Flash memory systems are well-known. Flash memory systems typically comprise one or more arrays of flash memory cells. The cells are organized into rows and columns within the array. Each row is activated by a word line, and each column is activated by a bitline. Thus, a particular flash memory cell is accessed for either read or write operations by asserting a specific word line and a specific bitline.
In some prior art systems, during read operations, the bitline will be precharged by a bitline regulator to a bias voltage accurately in a very short period. This increases the speed and accuracy of the system.
As flash memory systems have become faster, the prior art bitline regulators have become limiting factors in how fast the system can run. For example, if a flash memory system operates at 100 MHz or faster, the bitline regulator must precharge the bitline in 1 ns or less. Prior art bitline regulators are unable to operate at this speed.
Some examples of prior art bitline regulators include those that utilize a Vt clamp, an operational amplifier, or an NMOS follower. These prior art systems are unable to operate accurately at higher speeds.
What is needed is an improved bitline regulator design that can operate at high speeds. What is further needed is a bitline regulator that can be automatically trimmed during operation of the memory system as operating conditions change and processes change.